Useful design equations for the PT2399

The PT2399 datasheet gives some data showing the relationship between the resistor on pin 6, the clock frequency, and the delay time. Unfortunately, it doesn’t offer any design equations relating these three variables. So, can we derive some? Yes, we can! They’re all included here.

First, a quick summary of what I’ve learned, if you want to cut to the chase:

Delay msecs = (11.46 * Resistance KΩ) + 29.70
Delay msecs = (683.21 / Clock Freq MHz) + 0.08
Delay msecs = (683.21 * Clock Period usecs) + 0.08
Delay msecs = (28.65/Current mA) + 29.70
Current mA = 28.65 / (Delay msecs - 29.70)

The information we’ve got is in a table on page eight of the datasheet, shown at the foot of the page. It also gives a value for total harmonic distortion (THD) but I’m not interested in that. Basically, the PT2399 sounds crunchier and crunchier the longer the delay gets. No surprises there.

The datasheet is vague about how exactly the PT2399 works, but it suggests that the audio is digitised, then clocked into a 44K RAM by a variable frequency VCO clock, and then converted back to analog at the far end.

The first hurdle is to see whether the response of the Clock VCO is linear. In the datasheet circuit, the clock VCO is controlled by a resistor connected from pin 6 to ground. If we plot the data they give us (red crosses), we get the two graphs shown below.

So the good news is that the relationship of resistance and delay time is linear! We can use a least squares method to find a line of best fit (in green on the right graph). After getting the computer to do the numbers, this gives us:

Delay msecs = (11.46 * Resistance KΩ) + 29.70

Note that Delay is in msecs, and Resistance in KΩs, since that’s the numbers they gave us. Many people recommend a 50KΩ potentiometer attached to pin 6 as a Delay Time control, and this gives a maximum delay of 600msecs according to the equation above.

Clock Frequency and delay time

So what’s the relationship of the clock frequency and the delay time? Again, we can plot the data they give us, and we can see that the Clock Freq / Delay graph has a clear Y = 1/X shape. This might suggest that we should plot 1/frequency instead. 1/frequency is the clock period, and when we plot that, we get a nice linear graph.

Using the same best-fit method as before, we get:

Delay msecs = (683.21 * Period usecs) + 0.08

Period is in usecs (e.g. 1/clock in MHz), Delay is in msecs. It’s the same as the graph. From this equation, we can see that:

Delay msecs = (683.21 / Clock Freq MHz) + 0.08

The constant of 0.08 is a bit pointless since it’s so small (80 microseconds!), and you can’t go that fast anyway.

VCO sink current

The suspicion is (since Princeton Technology won’t tell us) that the current drawn from pin 6 controls the VCO frequency, rather than the resistance directly. We know from Ohm’s law that R=V/I, so we can replace the delay resistor in our previous equation. The voltage at pin 6 is nominally 2.5V, although it gets dragged down a bit (about 150mV) as the current increases. This gives us:

Delay msecs = (11.46 * 2.5 / Current mA) + 29.70 = (28.65 / Current mA) + 29.70

Note that Current is in mA, since R was in KΩ. We can rearrange this so we can find the required current for a given delay:

Current mA = 28.65 / (Delay msecs - 29.70)

Current is in mA, Delay is in msecs. The practical delay range of the chip is from about 35msecs to 600msecs, so this gives a current of between 5.4mA and 50uA.

The raw data from the PT2399 datasheet

Note that for one of the graphs above I also calculated the clock period, 1/Fclk.