The PT2399 datasheet gives some data showing the relationship between the resistor on pin 6, the clock frequency, and the delay time. Unfortunately, it doesn’t offer any design equations relating these three variables. So, can we derive some? Yes, we can! They’re all included here.
First, a quick summary of what I’ve learned, if you want to cut to the chase:
Delay msecs = (11.46 * Resistance KΩ) + 29.70 Delay msecs = (683.21 / Clock Freq MHz) + 0.08 Delay msecs = (683.21 * Clock Period usecs) + 0.08 Delay msecs = (28.65/Current mA) + 29.70 Current mA = 28.65 / (Delay msecs - 29.70)
The information we’ve got is in a table on page eight of the datasheet, shown at the foot of the page. It also gives a value for total harmonic distortion (THD) but I’m not interested in that. Basically, the PT2399 sounds crunchier and crunchier the longer the delay gets. No surprises there.
The datasheet is vague about how exactly the PT2399 works, but it suggests that the audio is digitised, then clocked into a 44K RAM by a variable frequency VCO clock, and then converted back to analog at the far end.
The first hurdle is to see whether the response of the Clock VCO is linear. In the datasheet circuit, the clock VCO is controlled by a resistor connected from pin 6 to ground. If we plot the data they give us (red crosses), we get the two graphs shown below.
So the good news is that the relationship of resistance and delay time is linear! We can use a least squares method to find a line of best fit (in green on the right graph). After getting the computer to do the numbers, this gives us:
Delay msecs = (11.46 * Resistance KΩ) + 29.70
Note that Delay is in msecs, and Resistance in KΩs, since that’s the numbers they gave us. Many people recommend a 50KΩ potentiometer attached to pin 6 as a Delay Time control, and this gives a maximum delay of 600msecs according to the equation above.
Clock Frequency and delay time
So what’s the relationship of the clock frequency and the delay time? Again, we can plot the data they give us, and we can see that the Clock Freq / Delay graph has a clear Y = 1/X shape. This might suggest that we should plot 1/frequency instead. 1/frequency is the clock period, and when we plot that, we get a nice linear graph.
Using the same best-fit method as before, we get:
Delay msecs = (683.21 * Period usecs) + 0.08
Period is in usecs (e.g. 1/clock in MHz), Delay is in msecs. It’s the same as the graph. From this equation, we can see that:
Delay msecs = (683.21 / Clock Freq MHz) + 0.08
The constant of 0.08 is a bit pointless since it’s so small (80 microseconds!), and you can’t go that fast anyway.
VCO sink current
The suspicion is (since Princeton Technology won’t tell us) that the current drawn from pin 6 controls the VCO frequency, rather than the resistance directly. We know from Ohm’s law that R=V/I, so we can replace the delay resistor in our previous equation. The voltage at pin 6 is nominally 2.5V, although it gets dragged down a bit (about 150mV) as the current increases. This gives us:
Delay msecs = (11.46 * 2.5 / Current mA) + 29.70 = (28.65 / Current mA) + 29.70
Note that Current is in mA, since R was in KΩ. We can rearrange this so we can find the required current for a given delay:
Current mA = 28.65 / (Delay msecs - 29.70)
Current is in mA, Delay is in msecs. The practical delay range of the chip is from about 35msecs to 600msecs, so this gives a current of between 5.4mA and 50uA.
The raw data from the PT2399 datasheet
Note that for one of the graphs above I also calculated the clock period, 1/Fclk.
| R | Fclk | Delay |
|---|---|---|
| 27.6 KΩ | 2 MHz | 342 msecs |
| 21.3 KΩ | 2.5 MHz | 273 msecs |
| 17.2 KΩ | 3 MHz | 228 msecs |
| 14.3 KΩ | 3.5 MHz | 196 msecs |
| 12.1 KΩ | 4 MHz | 171 msecs |
| 10.5 KΩ | 4.5 MHz | 151 msecs |
| 9.2 KΩ | 5 MHz | 136.6 msecs |
| 8.2 KΩ | 5.5 MHz | 124.1 msecs |
| 7.2 KΩ | 6 MHz | 113.7 msecs |
| 6.4 KΩ | 6.5 MHz | 104.3 msecs |
| 5.8 KΩ | 7 MHz | 97.1 msecs |
| 5.4 KΩ | 7.5 MHz | 92.2 msecs |
| 4.9 KΩ | 8 MHz | 86.3 msecs |
| 4.5 KΩ | 8.5 MHz | 81 msecs |
| 4 KΩ | 9 MHz | 75.9 msecs |
| 3.4 KΩ | 10 MHz | 68.1 msecs |
| 2.8 KΩ | 11 MHz | 61.6 msecs |
| 2.4 KΩ | 12 MHz | 56.6 msecs |
| 2 KΩ | 13 MHz | 52.3 msecs |
| 1.67 KΩ | 14 MHz | 48.1 msecs |
| 1.47 KΩ | 15 MHz | 45.8 msecs |
| 1.28 KΩ | 16 MHz | 43 msecs |
| 1.08 KΩ | 17 MHz | 40.6 msecs |
| 0.894 KΩ | 18 MHz | 38.5 msecs |
| 0.723 KΩ | 19 MHz | 36.6 msecs |
| 0.519 KΩ | 20 MHz | 34.4 msecs |
| 0.288 KΩ | 21 MHz | 32.6 msecs |
| 0.005 KΩ | 22 MHz | 31.3 msecs |
Thanks for this
Thank for the info!
You are indeed awesome. Why would they chose to make the information around their product (the PT2399 IC) so damn hard to understand and almost.as if thry dont want you to know these things?!
Time saving information. Thanks!
I’m thinking about running three PT2399 delays in parallel with a 3 phase modulation source to control the delay times… just for fun.
The LDR/resistor combination on pin 6 used in your PTWobble idea maybe fine for a one delay system but I would like something more linear and repeatable.
From your description of how the voltage varies on this pin it seems that it may be possible to use an active current sink instead of a resistor. Have you tried this or looked into it at all? I don’t have a PT2399 to play with.
Yes, you could use a current sink instead, and I have played with it. At one point, I was looking into Tap Tempo for the PT2399, and a current sink is a good way to do that (Ultimately I gave up on it because the delay times aren’t long enough to make it worth it). Simple current sinks tend not to be that linear, and better designs add more parts. PLus you also need to filter the signal coming from the TAPLFO or STOMPLFO or whatever, so that adds more parts too. The advantage of the LED/LDR is the LED can be driven directly and no filtering is needed.
Anyway, if it’s for modulation and the delay is going to be waving about all over the place, why does it need to be very linear? Do you think you’ll notice?
…”Anyway, if it’s for modulation and the delay is going to be waving about all over the place, why does it need to be very linear? Do you think you’ll notice?”
Absolutely no idea. But I suspect that one LDR will have different characteristics from another and LEDs are not always consistent in light output/mA… and then the variance in optical coupling. It’s not so much the need for linearity as consistency. Since the eventual chorus effect is intended to eliminate (or reduce) the cyclic modulation sound of a single delay chorus effect I would like to have all three delays varying identically but phase shifted by 120 degrees.
The matching may not be that important in practice but if I’m going to put in the effort I might as well remove that uncertainty from the outset… I would be kicking myself if it was quite criticaI and had to go back and redesign it.
The current sinks I imagine would just be an NPN transistor with emitter resistor to ground with base and emitter in a feedback loop of an op-amp.
“The current sinks I imagine would just be an NPN transistor with emitter resistor to ground with base and emitter in a feedback loop of an op-amp.”
Watch out for op-amp clipping with this design. If the PT2399 and a processor generating the LFO are running on 0-5V and the op-amp is running on 0-9V, you need to make sure the op-amp can drive its output close to ground. Something basic like the TL07x can only get to a volt or so from the rails, so the current source clips with voltages below a volt.
Thanks for the tip.
I tend to use the Microchip MCP6242 or MCP600x series op-amps when interfacing to 5V devices. They can run on 5V supplies and offer rail-to-rail input and output swings. Things are so much easier these days!!!
Well, have got a couple of the PT2399s running in parallel and summed with the input signal. It produces a richer chorus when the delays are modulated in antiphase compared to a single delay chorus. However, trying to get a variable rate 3 phase modulator is not so easy… I think a PIC with PWM outputs would be the most effective solution but maybe for another day.
The PT2399s are well suited to their intended applications but for comb filtering effects the minimum delay of 31ms is a bit limiting. I don’t suppose they offer other versions?…
Yes, there are some other versions, PT2395 for one if I remember rightly, but they’re not as straightforward to use. I think they maybe need external RAM. Perhaps you could use one to get a shorter delay. There are other similar chips (now obsolete but still available) by other manufacturers if you hunt about too.
“The datasheet is vague about how exactly the PT2399 works, but it suggests that the audio is digitised”.
Hilarious! The PT2399 documentation is so poor, we can’t even be sure whether it is analog or digital. For some years I had assumed it was a bucket brigade device (perhaps it is, who knows) !
We can be pretty sure, although we won’t get a solid confirmation. There’s a 44K RAM shown on the block diagram, so it’s definitely digital. The use of integrators and a high clock frequency suggests a Sigma-Delta type of ADC/DAC around the memory, so it’s probably a 1-bit delay.
Your’re right about the the PT2395 re. ext DRAM but it has a longer minimum delay even when over-clocked. The PT2396 has a shortest delay of 12.3ms with the recommended 2MHz clock and the (seemingly equivalent) Mitsubishi M65831 can be over-clocked up to 3MHz, but for flanging I would still need something shorter.
BBDs are really quite noisy and benefit immensely from companders.
A dsPIC solution would be the easiest solution for a wide range of delay times but to run two in parallel is not a very elegant.solution. Any better ideas?
You’re going to have to decide where you make your compromises. Otherwise you’re looking at a no-compromises design, which is going to be a codec and a processor and you do the whole thing digitally. You’ll get 100dB S/N, 96KHz sample rate, 24-bit audio, etc etc no compromises! And you can have as many separate LFOs and delay lines as you can be bothered to program and the RAM can stand. The number of parts will be small, and the physical size will be even smaller since you’ll only get parts like that in tiny SMD packages.
Any other solution is going to involve compromise – noise, complexity, something. BBDs are noisy. dsPIC is noisy, if you use the internal DAC. PT-series add distortion and don’t go short enough. You can’t have everything. You have to choose.
Fair comment.
I once saw a schematic (some 30 years ago) for a very simple delta-sigma conversion digital delay using common off-the-shelf chips plus a 64k x 1b DRAM (KM4164A-15). It had a suprising low chip count and nothing expensive. Obviously it wasn’t “studio quality” but better than the BBD equivalent and didn’t need such tight filtering.