This project is a development of my earlier VCADSR envelope generator. Whilst that chip had both GATE and TRIGGER inputs, this chip replaces the TRIGGER input with a MODE CV that allows selection of normal ADSR, Gated looping, or full LFO-style Looping modes.
Standard ADSR mode generates the shape you expect, and allows CV control of envelope depth and overall time.
Gated looping mode loops while the Gate is high. When the Gate goes low, the envelope goes to the Release stage.
LFO Looping mode loops all the time, acting like a highly versatile LFO.
The LOOPENV chip keeps the other features of the original VCADSR, like the LEVEL CV which controls the output level and can act as an ‘envelope depth’ control, and the TIME CV which shortens the overall time of the whole envelope. The TIME CV makes an excellent modulation input for either envelope modulation or LFO frequency modulation.
Full details are in the datasheet below, but the envelope times range from 1mS through to 10Secs, in 4 even decades, and all control voltages run from 0-5V.
There is also a digital input which selects either a ‘traditional’ exponential envelope shape, or a early-digital-era linear envelope.
Version 1B – a bug fix
After publishing this code, a small bug was discovered whereby the Gated Loop mode wouldn’t exit to the release stage correctly. Version 1B corrects this.
- Voltage-controlled envelope generator PIC 16F684 ASM code LOOPENV 1B
- Assembled LOOPENV1B HEX code from above file
- Circuit Diagram
- LOOPENV datasheet (includes circuit diagram and chip pinout)
Looping Envelope elsewhere on the web
Additionally, Rick also builds and sells completed modules based on my chips. You can find these on his Frequency Central LoopEnv page.